Tag Archives: verilog source code

Verilog Examples from Books Included With VeriLogger

One question that occasional pops up from customers is “What Verilog code examples do we ship with our simulator?”. VeriLogger ships with all the Verilog source code examples from two popular Verilog text books: Mano’s Digital Design and Minn’s FSM-Based Digital Design (with permission of the publishers). These examples are located under C:\SynaptiCAD\Examples\Examples_Book.

We also include some open-source examples (mainly taken from opencores.org) in C:\SynaptiCAD\Examples\VeriLogger. Finally, there’s some TestBencher-generated test bench examples located in C:\SynaptiCAD\Examples\TestBencher\Verilog (these last examples require a TestBencher license to fully be generated).