Monthly Archives: November 2012

Detecting infinite loops in Verilog processes

Because Verilog code has communicating concurrent processes, it’s much easier to accidentally write code that results in an infinite loop, and it’s harder to identify the cause of the infinite loop.

We’ve added an option to VeriLogger to automatically interrupt the simulation after a large number of delta cycles have taken place without advancing simulation time. By default, the delta cycle limit is set to 1000, but it can be changed using the simxloader option, –scd_max_delta=<limit>.

Here’s an example of an infinite loop between two zero-delayed assigns that would be interrupted automatically:

wire bw = cw === 1'bx ? b : cw+b;
assign cw = bw;
initial  #1 b = 1;

Delta cycles occur whenever a process is scheduled. Since the delta limit cycle is finite, it’s possible that some code could hit the limit even when there’s no infinite loop. For example, the code below would trigger the limit because the #0 time delay would cause the process to be rescheduled each iteration through the loop.

for (i=0; i < 4095; i = i + 1)
#0 ram[i] <= 0;

Of course, this code is not good code for many reasons (including efficiency, since it forces unnecessary reschedulings of the process) and should be written as below (which won’t trigger the limit):

for (i=0; i < 4095; i = i + 1)
ram[i] <= 0;

When the delta limit is hit, the simulator will interrupt the simulation and place the user at the simulator’s interactive command prompt so that the source of the infinite loop can be analyzed and debugged. Simulation can be resumed from the command prompt using any of the normal run commands.