Category Archives: Tips

Detecting infinite loops in Verilog processes

Because Verilog code has communicating concurrent processes, it’s much easier to accidentally write code that results in an infinite loop, and it’s harder to identify the cause of the infinite loop.

We’ve added an option to VeriLogger to automatically interrupt the simulation after a large number of delta cycles have taken place without advancing simulation time. By default, the delta cycle limit is set to 1000, but it can be changed using the simxloader option, –scd_max_delta=<limit>.

Here’s an example of an infinite loop between two zero-delayed assigns that would be interrupted automatically:

wire bw = cw === 1'bx ? b : cw+b;
assign cw = bw;
initial  #1 b = 1;

Delta cycles occur whenever a process is scheduled. Since the delta limit cycle is finite, it’s possible that some code could hit the limit even when there’s no infinite loop. For example, the code below would trigger the limit because the #0 time delay would cause the process to be rescheduled each iteration through the loop.

for (i=0; i < 4095; i = i + 1)
#0 ram[i] <= 0;

Of course, this code is not good code for many reasons (including efficiency, since it forces unnecessary reschedulings of the process) and should be written as below (which won’t trigger the limit):

for (i=0; i < 4095; i = i + 1)
ram[i] <= 0;

When the delta limit is hit, the simulator will interrupt the simulation and place the user at the simulator’s interactive command prompt so that the source of the infinite loop can be analyzed and debugged. Simulation can be resumed from the command prompt using any of the normal run commands.


Using Symbolic Libraries to Speed Up Verilog Compilation

Designs often reuse a common set of our Verilog source files. For example, when you’re designing using a particular family of FPGAs or ASICs, you will need to compile the vendor-provided Verilog source files for those parts. Instead of recompiling these files for each new design, you can compile them once into a symbolic library (sometimes referred to as a compiled library), then just reference that symbolic library in your designs. With this approach, you only need to recompile the vendor’s source files when you update your simulator to a newer version.

Cells and Snapshots

A symbolic library contains cells and snapshots. Cells represent the definitions for objects such as modules and User-Defined Primitives (UDPs) that are created when source files are compiled into a library. Snapshots are created during simulation elaboration and represent a fully built “simulation” that can be executed.

Within a library, cell and snapshot names must be unique and any attempt to compile a cell into a library that already contains a cell of that name will cause the original cell to be overwritten. However, cells and snapshots of the same name can exist in different libraries.

Creating Symbolic Libraries

In most Verilog compilers, a symbolic library is given both a logical name (e.g. “work”) and a physical name that indicates it’s storage location (e.g. “c:\myproject\scd_work”). The logical name is used when referring to a symbolic library in the source code or when passing a library name as a command-line option to the verilog compiler, so that the source code and script files don’t have to depend on the library’s location on a particular computer.  The physical name is only used to specify the location of the symbolic library (and typically only when the library is first created). The mapping between these two names is specified using a command-line library tool that can create and manipulate symbolic libraries and the resulting mappings are stored into a “map file”. In simx, for example, this command-line tool is called simxlib. In both Mentor Graphics ModelSim and Aldec Active HDL, the library tool is called vlib.

Work: the Default Symbolic Library

By default, sources files will be compiled into a compiled library with the symbolic name of “work, unless a different destination library is specified via the --work <destination_library_name> compiler option. Also by default, the work library will be mapped to a subdirectory of the current working directory called scd_work, unless a map file is passed to the compiler that specifies a different physical path name for the library.  This default mapping will be written into a default map file called scd.lib which simx will subsequently load automatically whenever simulations are run from this directory. The above defaults allow simx to be used without having to worry about symbolic libraries, if you don’t plan to take advantage of them to avoid re-compiling shared Verilog code.

By contrast, some compilers require you to create at least one symbolic library using their library tool before you can compile code with these simulators, so if you use BugHunter to compile code with ModelSim or ActiveHDL, you will note that it first launches vlib to create a work library before it launches the actual Verilog or VHDL compilers (aka vlog or vsim) for these simulators.

Example Commands for Creating and Using Symbolic Libraries

To compile test1.v and add it’s contents to the default library called “work”, you can either directly specify the work library with the -work option:

simx --work work test1.v

or let the simulator just use work by default:

simx test1.v

In the above commands, the work library will be automatically created in a subdirectory called scd_work if it doesn’t already exist.

To create a library with the logical name vendor1 located at c:\vendor1 and compile a set of files into this library, use the following commands:

simxlib --create c:\vendor1
simx --work vendor1 test1.v test2.v test3.v

The above commands also create a scd.lib file in the current directory with the following contents:

DEFINE vendor1 c:/vendor1

This line says that the logical library name vendor1 maps to the physical library located at c:\vendor1.

Debugging Verilog Parameter errors

Whenever you’re working with a large Verilog design, there’s likely to be a significant use of params (and localparams), especially when you’re stitching together IP blocks from one or more third party vendors. Params are often defined as mathematical expressions and a param’s final compiled value can often be quite difficult to figure out just by looking at the Verilog code because the expressions are scattered throughout the design hierarchy.

A parameter with an undesired value can lead to both very obvious errors (mismatch in size of a wire to a port) or to very subtle errors (e.g. a parameter used to count a number of clock cycles before reporting an error is set too large to ever get triggered). For this reason, it’s a good idea to verify the values of parameters at the interfaces between code you write and any third party IP you’re using prior to running simulations.

The quickest way to verify the parameter values is to compile (build) the design, then navigate through the resulting graphical design hierarchy tree which shows the computed values of the parameters for each IP instance. You can search for all instances of a module in a tree by entering the name of the module prefixed by a “.” (e.g. “.foo” where foo is the name of the module) in the quick search box. Under each instance node in the tree is a sub-folder called Constants that lists all the top-level parameters for that instance and their compile-computed values. You can quickly scan this list to look for any parameter values that appear to be out of whack.

One final note: scanning through the computed values for internal params in a 3rd party IP is also useful in gaining better insight into how the IP works as key design details are often abstracted into param values. This can help you avoid trying to use the IP in a way that it wasn’t coded to work properly.

Detecting Races with VeriLogger

It’s easy to accidentally introduced “races” into Verilog, especially when you’re working with just one simulator. Since the Verilog language purposely doesn’t specify a particular order for execution of parallel process blocks, these races will frequently lead to different simulation results when a design is simulated by simulators from different vendors. VeriLogger has always been pretty useful for detecting simulation races, because our BugHunter GUI allows you to switch back and forth between our simulator (Simx) and 3rd party simulations (e.g. ModelSim, NcSim, ActivHdl, and VCS), making it easier to find such races. But this still required you to have access to other simulators to detect the races.

Over the past few months, while working with some of our customers who were “qualifying” our simulator with their existing designs, several such races have been found in the designs. Each time we encountered a simulation difference between us and a 3rd party simulator they were using, we had to determine whether the problem was a bug in our simulator, a bug in the other simulator, or a race in the design.

To speed this process up, we added several new command-line options to enable our simulator to change our default ordering of process execution and also to handle a few cases where the Verilog Language Reference Manual was vague enough about how a situation should be handled that different 3rd party vendors have chosen different ways to handle those siutations. By default, our simulator most closely models the process ordering used by Cadence’s Ncsim, so we added options to match the ordering used by Mentor’s ModelSim and Aldec ActiveHdl. We also added an option to randomize the ordering which given a few simulation runs should generally detect a problematic race in just about any design. The new options are:

–scd_invert_queue: inverts order in which “same priority” events in the event queue are evaluated.

–scd_randomize_queue: randomizes the order in which “same priority” events are evaluated.

–scd_mtilike_queue: evaluates event queue similar to ModelSim/ActiveHdl.

–scd_immediate_sensitivity: makes event control statements at the beginning of a process immediately sensitive after simulation initialization.

–scd_mtilike_dist_functions: makes $random and $dist functions behave like ModelSim/ActiveHdl instead of like NcSim.

What all this amounts to is, although our original goal was to make it easier to qualify our simulator as being functionally correct, we’ve ended up creating a new way to quickly detect races in your designs, as well. Finding these races can save you a lot of headaches down the road, especially if you sell IP to customers who use different simulators from the ones you normally work with!

BugHunter Pro: swapping between different simulators

In this blog, I’ll be discussing the evolving architecture of VeriLogger, as well as sharing tips on how to get the most out of the environment. Today I’ll be discussing ways to change what simulator is used by the Verilogger environment to simulate a design.

VeriLogger actually consists of two separate programs: BugHunter Pro , a graphical debugger/testbench generator (executable filename is syncad.exe) and a Verilog simulator. The default Verilog simulator used by BugHunter is SynaptiCAD’s Sim Extreme, a compiled-code Verilog 2001 simulator (executable filename is simx.exe).

BugHunter supports debugging with all the major Verilog and VHDL simulators and it can be easily configured via the GUI to swap out which simulator it uses for performing simulations. In Verilog, it’s fairly easy to accidentally introduce race conditions into your code that will cause simulation output to be different across different simulators, so it’s not a bad idea when you have access to multiple simulators to run your design through multiple simulators and compare the output. This is particularly important when you’re creating IP that is going to customers who may use a different simulator than you used to design your IP.

The first way to set the simulator used by BugHunter is via the command line when BugHunter is started. For example:

syncad -p bhp -S verilogger_extreme

launches the product BugHunter (-p bhp) with the verilog_extreme simulator as the default simulator for new projects.

To override the above default setting for new projects using the GUI, select the menu option Project>Default Project Simulation Properties, click the Settings Template radio button, select the Verilog tab, then set the Simulator Type to the desired simulator.

To change the simulator used for an existing project, select the menu option Project>Project Simulation Properties, click the Verilog tab, and pick the desired simulator from the Simulator Type control.

Debugging information such as breakpoints and which signals to watch in the waveform window are stored in a simulator-independent format inside your project, so this information is portable across simulators. Common compilation options such as include and library paths are also stored in a portable format.

Project files can store multiple configurations, with each configuration storing a list of settings on how to compile the project (what compiler to use and what compilation options). Configurations make it easy to switch between simulators or to simply switch between a “debug simulation” where you build a slower simulation that is fully debuggable versus a “fast simulation” that runs quickly but doesn’t make as much debug info accessible. To create a configuration, use the Project Simulation Properties to set the desired simulator and compilation options, then press the Add button to create the new configuration and give it a name.