Tag Archives: Verilog examples

Verilog Examples from Books Included With VeriLogger

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One question that occasional pops up from customers is “What Verilog code examples do we ship with our simulator?”. VeriLogger ships with all the Verilog source code examples from two popular Verilog text books: Mano’s Digital Design and Minn’s FSM-Based Digital Design (with permission of the publishers). These examples are located under C:\SynaptiCAD\Examples\Examples_Book.

We also include some open-source examples (mainly taken from opencores.org) in C:\SynaptiCAD\Examples\VeriLogger. Finally, there’s some TestBencher-generated test bench examples located in C:\SynaptiCAD\Examples\TestBencher\Verilog (these last examples require a TestBencher license to fully be generated).

Verilog Books and VeriLogger

If you’re learning Verilog for the first time, you may be interested in several text books that now ship with an included VeriLogger disk and introductory Verilog source files and projects that are “ready to compile”. Here’s a partial listing as of the date of this posting in order of most recently published/updated:

FSM-based Digital Design using Verilog HDL by Peter Minns and Ian Elliott, 2008

Digital Design (4th Edition) by Morris Mano & Michael Ciletti, 2006
Digital Design (3rd Edition) by Morris Mano, 2001

The Verilog Hardware Description Language by Thomas & Moorby, 5th edition (2002)

If you obtain one of the older books, you should probably download the most recent version of the simulator for best performance.