Debugging Verilog Parameter errors

Whenever you’re working with a large Verilog design, there’s likely to be a significant use of params (and localparams), especially when you’re stitching together IP blocks from one or more third party vendors. Params are often defined as mathematical expressions and a param’s final compiled value can often be quite difficult to figure out just by looking at the Verilog code because the expressions are scattered throughout the design hierarchy.

A parameter with an undesired value can lead to both very obvious errors (mismatch in size of a wire to a port) or to very subtle errors (e.g. a parameter used to count a number of clock cycles before reporting an error is set too large to ever get triggered). For this reason, it’s a good idea to verify the values of parameters at the interfaces between code you write and any third party IP you’re using prior to running simulations.

The quickest way to verify the parameter values is to compile (build) the design, then navigate through the resulting graphical design hierarchy tree which shows the computed values of the parameters for each IP instance. You can search for all instances of a module in a tree by entering the name of the module prefixed by a “.” (e.g. “.foo” where foo is the name of the module) in the quick search box. Under each instance node in the tree is a sub-folder called Constants that lists all the top-level parameters for that instance and their compile-computed values. You can quickly scan this list to look for any parameter values that appear to be out of whack.

One final note: scanning through the computed values for internal params in a 3rd party IP is also useful in gaining better insight into how the IP works as key design details are often abstracted into param values. This can help you avoid trying to use the IP in a way that it wasn’t coded to work properly.

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