This site was down for a bit during re-hosting, then it was back up, but not accessible internally for me! Needless to say, this made it difficult for us to make new postings. But all’s well now, so let the postings begin…
The Verilog 2005 standard introduced a new feature to support protected intellectual property. This feature allows IP vendors to deliver models in encrypted form. Vendors may choose to encrypt entire files, or only encrypt parts of a model. You can choose to encrypt entire files, or only encrypt parts of a model. Xilinx has begun using this method to encrypt it’s latest IP models, since the resulting models simulate faster than object-code model equivalents (e.g. SmartModels).
The simplest way to encrypt your source code is to use VeriLogger’s public key. This will allow any VeriLogger user to compile and use the encrypted model by simply adding the file to their project. VeriLogger will compile and simulate using the encrypted code, but the user will not have access to any of the source code. You can also encrypt a file with a public key of own, then provide this key to consumers of your IP so that they can use the IP with any simulator that supports the encryption standard.
Encryption Steps
Before encrypting your source, test the unencrypted source code with VeriLogger Extreme to ensure that it compiles without errors. Since the end-user of your IP will not have access to the source code, they will be unable to fix any problems, and error messages in encrypted sections of code will be useless.
To create an encrypted file, perform the steps below:
1. Add `pragma protect directives to the source to delimit which sections to encrypt. Anything between a `pragma protect begin line and a `pragma protect end will be encrypted. Anything outside these directives will be copied verbatim to the output file.
2. Run the simulation generator, simxgen, to encrypt a source file called sram.v:
simxgen +protect sram.v
This will generate an encrypted file called sram.vp. The .vp file extension indicates an encrypted verilog file.
For details on how to create and use your own encryption keys or how to encrypt a model with multiple keys, see the section on Verilog Protected Envelopes in the Verilogger online help.
If you’re learning Verilog for the first time, you may be interested in several text books that now ship with an included VeriLogger disk and introductory Verilog source files and projects that are “ready to compile”. Here’s a partial listing as of the date of this posting in order of most recently published/updated:
FSM-based Digital Design using Verilog HDL by Peter Minns and Ian Elliott, 2008
Digital Design (4th Edition) by Morris Mano & Michael Ciletti, 2006
Digital Design (3rd Edition) by Morris Mano, 2001
The Verilog Hardware Description Language by Thomas & Moorby, 5th edition (2002)
If you obtain one of the older books, you should probably download the most recent version of the simulator for best performance.