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	<title>Comments for VeriLogger</title>
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	<description>Simplifying the design of digital systems</description>
	<pubDate>Wed, 08 Sep 2010 14:45:28 +0000</pubDate>
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		<title>Comment on BugHunter Preparses before Simulator Builds by DanNotestein</title>
		<link>http://www.verilogger.com/?p=6#comment-10</link>
		<dc:creator>DanNotestein</dc:creator>
		<pubDate>Fri, 16 Jul 2010 22:09:41 +0000</pubDate>
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		<description>The above also means you can start selecting signals to watch via the project window as soon as the preparse finishes, before the simulation compiler has finished compiling (this is mostly useful if you're compiling a vary large simulation).</description>
		<content:encoded><![CDATA[<p>The above also means you can start selecting signals to watch via the project window as soon as the preparse finishes, before the simulation compiler has finished compiling (this is mostly useful if you&#8217;re compiling a vary large simulation).</p>
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